1. Field of the Invention
The present invention relates to a method and apparatus for stuck fault testing an oscillator and more particularly to method and apparatus for stuck fault testing an oscillator adapted for use with a Level Sensitive Scan Design (LSSD) system and testing technique of the type disclosed and defined in U.S. Pat. Nos. 3,783,254, 3,761,695, 3,784,907 and 4,268,903 and of common assignee.
2. Description of the Prior Art
Due to the complexity and the extremely great number of circuit functions contained on a single large scale integrated (LSI) device or chip, the LSSD system and testing technique have been widely used. An oscillator is susceptible to stuck faults or permanent static bit failures where a clock oscillator signal is fixed at either a logical one "1" or a logical zero "0."
U.S. Pat. No. 4,268,903 issued May 19, 1981 and of common assignee generally discloses the LSSD system and testing technique and a computer system including a maintenance interface compatible with LSSD design for synchronizing the operation of a service processor and a central pro- cessing unit. The disclosure of U.S. Pat. No. 4,268,903 is incorporated herein by reference.
Various testing techniques have been employed to identify stuck faults in oscillators. Many testing techniques utilize a separate reference pulse which requires additional logic to generate and that is also subject to failure. Examples of such testing techniques are disclosed in U.S. Pat. Nos. 4,374,361, 4,399,412, 4,467,285 and a publication entitled "PULSE CHECKING CIRCUIT" by P. J Veneziano, IBM Technical Disclosure Bulletin, Vol. 9, No. Oct. 5, 1966, p. 473. Other significant disadvantages of the above and many of the known testing methods are that LSSD compatibility is not provided and a special reporting logic is required.
Many testing methods that are compatible with LSSD testing techniques disable the system oscillator during diagnostic subroutines so that an oscillator stuck fault cannot be identified.
For example, U.S. Pat. No. 4,542,509 discloses a method and apparatus for fault testing a clock distribution network that includes a plurality of clock signal lines for distributing a clock signal from a system oscillator. The fault testing apparatus includes a test latch for storing either a logical value one "1" or a logical value "0" and a decoder for connecting any one of the clock signal lines to the test latch. During the fault testing method the system oscillator is effectively disconnected from the clock distribution network under test.
A need exists for a method and apparatus for detecting oscillator stuck faults that facilitates error reporting with the LSSD scan function and that does not require additional input/output pins or other special changes to individual chips.